High-Speed Continuous Wavelet Transform Processor for Vital Signal Measurement Using Frequency-Modulated Continuous Wave Radar

This paper proposes a high-speed continuous wavelet transform (CWT) processor to analyze vital signals extracted from a frequency-modulated continuous wave (FMCW) radar sensor. The proposed CWT processor consists of a fast Fourier transform (FFT) module, complex multiplier module, and inverse FFT (I...

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Published inSensors (Basel, Switzerland) Vol. 22; no. 8; p. 3073
Main Authors Bae, Chanhee, Lee, Seongjoo, Jung, Yunho
Format Journal Article
LanguageEnglish
Published Switzerland MDPI AG 16.04.2022
MDPI
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Summary:This paper proposes a high-speed continuous wavelet transform (CWT) processor to analyze vital signals extracted from a frequency-modulated continuous wave (FMCW) radar sensor. The proposed CWT processor consists of a fast Fourier transform (FFT) module, complex multiplier module, and inverse FFT (IFFT) module. For high-throughput processing, the FFT and IFFT modules are designed with the pipeline FFT architecture of radix-2 single-path delay feedback (R2SDF) and mixed-radix multipath delay commutator (MRMDC) architecture, respectively. In addition, the IFFT module and the complex multiplier module perform a four-channel operation to reduce the processing time from repeated operations. Simultaneously, the MRMDC IFFT module minimizes the circuit area by reducing the number of non-trivial multipliers by using a mixed-radix algorithm. In addition, the proposed CWT processor can support variable lengths of 8, 16, 32, 64, 128, 256, 512, and 1024 to analyze various vital signals. The proposed CWT processor was implemented in a field-programmable gate array (FPGA) device and verified through the measurement of heartbeat and respiration from an FMCW radar sensor. Experimental results showed that the proposed CWT processor can reduce the processing time by 48.4-fold and 40.7-fold compared to MATLAB software with Intel i7 CPU. Moreover, it can be confirmed that the proposed CWT processor can reduce the processing time by 73.3% compared to previous FPGA-based implementations.
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ISSN:1424-8220
1424-8220
DOI:10.3390/s22083073