A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer

• Published in: IEEE journal of solid-state circuits Vol. 40; no. 2; pp. 462 - 471
• Main Authors: Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Conroy, C.S.G., Beomsup Kim
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.02.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adaptive equalizer; Adaptive equalizers; Applied sciences; Attachment; Bit error rate; Channels; Circuits; clock data recovery (CDR); Clocks; CMOS; CMOS technology; Delay; Design. Technologies. Operation analysis. Testing; Electronic equipment and fabrication. Passive components, printed wiring boards, connectics; Electronics; Equalizers; Exact sciences and technology; High speed; Integrated circuits; Jitter; Least squares approximation; Power supplies; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; serial-link transceiver; Transceivers; Timing jitter; Multiplexing; Serial transmission; Mode coupling; Bit error rate; Power supply; Equalizer; Clock; Transceiver; Clock recovery; clock data recovery (CDR); Least squares method; Complementary MOS technology; serial-link transceiver; Adaptive equalizer
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2004.841037

This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) adaptive equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.