Analysis and modeling of layout scaling in silicon integrated stacked transformers

The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic...

Full description

Saved in:
Bibliographic Details
Published inIEEE transactions on microwave theory and techniques Vol. 54; no. 5; pp. 2203 - 2210
Main Authors Biondi, T., Scuderi, A., Ragonese, E., Palmisano, G.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.05.2006
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss). Based on this analysis, a wideband lumped model is developed, whose parameters are related to layout and technological data through closed-form expressions. Model accuracy is demonstrated by comparing simulated and measured S-parameters, coil inductance, magnetic coupling coefficient, and maximum available gain of several transformers with scaled layout geometry. The self-resonance frequency is also employed as a figure-of-merit to demonstrate model accuracy at very high frequency.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9480
1557-9670
DOI:10.1109/TMTT.2006.872788