Analysis and modeling of layout scaling in silicon integrated stacked transformers
The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic...
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Published in | IEEE transactions on microwave theory and techniques Vol. 54; no. 5; pp. 2203 - 2210 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.05.2006
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | The analysis and modeling of monolithic stacked transformers fabricated in a high-speed silicon bipolar technology is addressed. On-wafer experimental measurements are employed to investigate the effect of layout scaling on transformer performance parameters (i.e., self-resonance frequency, magnetic coupling coefficient, and insertion loss). Based on this analysis, a wideband lumped model is developed, whose parameters are related to layout and technological data through closed-form expressions. Model accuracy is demonstrated by comparing simulated and measured S-parameters, coil inductance, magnetic coupling coefficient, and maximum available gain of several transformers with scaled layout geometry. The self-resonance frequency is also employed as a figure-of-merit to demonstrate model accuracy at very high frequency. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0018-9480 1557-9670 |
DOI: | 10.1109/TMTT.2006.872788 |