A novel SET/MOSFET hybrid static memory cell design

• Published in: IEEE transactions on nanotechnology Vol. 3; no. 3; pp. 377 - 382
• Main Authors: LEE, Bong-Hoon, JEONG, Yoon-Ha
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2004; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Blocking; Circuits; CMOS logic circuits; CMOS memory circuits; CMOS technology; Conductance; Design engineering; Electronics; Exact sciences and technology; Fabrication; FETs; Integrated circuits; Integrated circuits by function (including memories and processors); Magnetic and optical mass memories; Molecular electronics, nanoelectronics; MOSFET circuits; MOSFETs; Nanotechnology; Read-write memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Simulation; Single electron transistors; SRAM chips; Storage and reproduction of information; Tunneling; Performance evaluation; Memory devices; MOSFET; Negative differential conductivity; SRAM chips; High density; Manufacturing process; Integrated circuit; Static storage; Nanoelectronics; Single electron transistors
• ISSN: 1536-125X; 1941-0085
• DOI: 10.1109/TNANO.2004.828581

In this paper, a single electron transistor (SET)/metal-oxide-semiconductor field effect transistor (MOSFET)-based static memory cell is proposed. The negative differential conductance (NDC) characteristics of the SET block help us establish the static memory cell circuits more compactly than those in conventional technologies. The proposed memory cell consists of one MOSFET and two back-to-back connected SET blocks exhibiting the NDC. The peak-to-valley current ratio of the SET block is above four with C/sub G/=5.4C/sub T/ (C/sub T/=0.1 aF) at T=77K. The read and write operations of the proposed memory cell were validated with SET/MOSFET hybrid simulations at T=77 K. Even though the fabrication process that integrates MOSFET devices and SET blocks with NDC is not yet available, these results suggest that the proposed SET/MOSFET hybrid static memory cell is suitable for a high-density memory system.