SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

• Published in: IEEE journal of solid-state circuits Vol. 40; no. 4; pp. 895 - 901
• Main Authors: Zhang, K., Bhattacharya, U., Zhanping Chen, Hamzaoglu, F., Murray, D., Vallepalli, N., Yih Wang, Zheng, B., Bohr, M.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.04.2005; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit stability; Circuits; CMOS; CMOS technology; Degradation; Design optimization; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuit technology; Integrated circuits; Integrated circuits by function (including memories and processors); Leakage; Leakage reduction; Power supplies; Random access memory; Reduction; Semiconductor devices; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Sleep; sleep transistor; SRAM; Static random access memory; Transistors; Very large scale integration; Voltage control; weak-write test mode; Low voltage; Static random access memory; Complementary MOS technology; Random access memory; Integrated circuit; Leakage reduction; Programmable circuit; weak-write test mode; Transistor; Voltage control; SRAM; sleep transistor
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2004.842846

A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-/spl mu/m/sup 2/ 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5/spl times/ while maintaining the integrity of stored data.