Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory

• Published in: IEEE journal of solid-state circuits Vol. 39; no. 11; pp. 2014 - 2023
• Main Authors: Le, B.Q., Achter, M., Chin Ghee Chng, Xin Guo, Cleveland, L., Pau-Ling Chen, Van Buskirk, M., Dutton, R.W.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2004; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuits; CMOS; CMOS technology; Costs; Detection; Disturbances; Electric potential; Electronics; Exact sciences and technology; Feedback; Flash memory; Flash memory (computers); Integrated circuits; Integrated circuits by function (including memories and processors); Leakage current; Low voltage; Power supplies; Random access memory; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Semiconductors; Stores; Threshold voltage; Voltage; Performance evaluation; Sensing techniques; Access time; virtual-ground memory 1.8-V flash memory; Experimental result; Flash memory; Virtual memory; Integrated circuit; 2-bit-per-cell memory; SPICE; Numerical simulation; Leakage current; Control method; CMOS integrated circuits; Differential method; Computer aided design
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2004.835814

Fast and accurate read operation in 1.8-V 2-bit-per-cell virtual-ground flash memories requires techniques to substantially reduce the read margin loss due to the side-leakage current and the complementary-bit disturbance. The read margin loss caused by the combination effect of these two disturbance mechanisms is serious enough to eliminate the read margin window, which is already small when the power supply voltage is about 1.8 V and when a memory cell stores 2 bits. This paper introduces for the first time the sense current recovery technique to counteract the side-leakage current effect and the differential feedback cascoded bitline control technique to minimize the complementary-bit disturbance. A 1.8-V 256-Mb 2-bit-per-cell virtual-ground flash memory employing the two techniques has been integrated using 0.13-/spl mu/m CMOS technology. These two sensing techniques are essential for the memory to achieve 49-ns initial read access and 200-MHz internal burst read access. The die size is 52 mm/sup 2/ and the cell size is 0.121 /spl mu/m/sup 2/.