An SRAM design using dual threshold voltage transistors and low-power quenchers

• Published in: IEEE journal of solid-state circuits Vol. 38; no. 10; pp. 1712 - 1720
• Main Authors: Wang, Chua-Chin, Lee, Po-Ming, Chen, Kuo-Long
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2003; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Access time; CMOS process; CMOS technology; Current supplies; Devices; Driver circuits; Electric potential; Field programmable gate arrays; Latches; MOSFETs; Oscillations; Portable computers; Random access memory; Semiconductor devices; Static random access memory; Threshold voltage; Transistors
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2003.817254

Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit-lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Also, the unwanted oscillation of the output bitlines of memories caused by large currents in bitlines is reduced by adding two back-to-back quenchers. The proposed quenchers not only prevent oscillation, but also reduce the idle power consumption when the memory cells are not activated by wordline signals. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAMs are feasible.