A 14-b linear capacitor self-trimming pipelined ADC

• Published in: IEEE journal of solid-state circuits Vol. 39; no. 11; pp. 2046 - 2051
• Main Authors: Seung-Tak Ryu, Ray, S., Bang-Sup Song, Gyu-Hyeong Cho, Bacrania, K.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.11.2004; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Analog-digital conversion; Applied sciences; Calibration; Capacitors; Circuit properties; CMOS; CMOS technology; Correlation; Digital-analog conversion; Dithering; Dithers; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Feedback loop; Noise levels; Operational amplifiers; Performance gain; Prototypes; Signal convertors; Testing, measurement, noise and reliability; Voltage; Performance evaluation; Waveform; Prototype; self trimming; Feedback regulation; Calibration; pipelined ADC; Experimental study; Chip; Implementation; Pipeline; Angle modulation; Experimental result; AD converter; Complementary MOS technology; Reference voltage; Pseudorandom sequence
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2004.835823

The capacitor mismatch in a 1.5-b/stage pipelined ADC is background calibrated in the analog domain using a pseudorandom (PN) dithering concept. The reference voltage added/subtracted during the normal operation is used as a dither to PN-modulate the mismatch error so that it can be embedded into the residue and be recovered later by correlating with the same PN sequence. Six MSB stages are simultaneously calibrated using separate zero-forcing feedback loops. The signal-subtracted analog PN correlation shortens the calibration time by one order. A 4.2/spl times/3.8 mm/sup 2/ prototype chip in 0.18-/spl mu/m CMOS exhibits /spl plusmn/1 LSB INL at 14 b and 84 dB SFDR at 30 MS/s, and consumes 350 mW at 3 V.