Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET

• Published in: IEEE transactions on electron devices Vol. 55; no. 8; pp. 2134 - 2141
• Main Authors: Khan, H.R., Mamaluy, D., Vasileska, D.
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.08.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Contact block reduction (CBR) method; Devices; Electronics; Exact sciences and technology; FinFET; Gates; Leakage current; Matrices; Nanostructure; process variation; quantum transport; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Simulation; slow corner analysis; Swing; Threshold voltage; Transistors; Gate current; Performance evaluation; Voltage threshold; MOSFET; Polycrystal; FinFET; Self consistency; Transistor gate; Dual gate transistor; Contact block reduction (CBR) method; Optimization; slow corner analysis; Self aligned technology; Reduction method; Work function; Gate oxide; process variation; Drain current; Leakage current; Barrier height; Simulator; Room temperature; Quantum transport; Damaging
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2008.925937

We examined the influence of process variation on device performance of the optimized 10-nm FinFET device using a fully self-consistent quantum-mechanical transport simulator based on the contact block reduction method. Sensitivity of the on-current, leakage currents, threshold voltage, drain-induced barrier lowering, and subthreshold swing for the optimized FinFET to process variation at room temperature have been investigated. Subthreshold source-to-drain leakage current is found to be the most sensitive parameter to process variation. Gate leakage current has been analyzed for both poly-Si gates and gates with the work function of 4.35 eV. For poly-Si gates, the gate leakage is found to influence the subthreshold swing below or at a gate oxide thickness of 1 nm. Device performance has also been analyzed at ldquoslow processrdquo corner to estimate the worst case degradation in performance matrices of the considered nano-FinFET.