Tunnel DCIV extraction of dopant-impurity concentration, oxide thickness, and length in the channel and extension regions of ultrathin gate-oxide MOS transistors

A methodology is described for extracting, between the source and drain, the spatial variations of surface dopant-impurity concentration and oxide thickness in the channel, drain/extension and source/extension regions using experimental tunnel direct current current-voltage data of the drain, source...

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Bibliographic Details
Published inIEEE transactions on electron devices Vol. 52; no. 7; pp. 1548 - 1554
Main Authors Jie, B.B., Chih-Tang Sah
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.07.2005
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:A methodology is described for extracting, between the source and drain, the spatial variations of surface dopant-impurity concentration and oxide thickness in the channel, drain/extension and source/extension regions using experimental tunnel direct current current-voltage data of the drain, source, and basewell terminal currents versus the gate/base voltage. An example is given using an pMOS transistor with W/L=10 /spl mu/m/0.3 /spl mu/m fabricated by a factory 100-nm technology. Zeroth (constant values) and first-order (linear variation with position) representation formulas are used for the impurity concentration and oxide thickness to fit the experimental data, which also give the electrical lengths of the three regions.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2005.850623