Optimal Design of Triple-Gate Devices for High-Performance and Low-Power Applications

• Published in: IEEE transactions on electron devices Vol. 55; no. 9; pp. 2423 - 2428
• Main Authors: CHIANG, Meng-Hsueh, LIN, Jeng-Nan, KIM, Keunwoo, CHUANG, Ching-Te
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.09.2008; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Asymmetry; Circuits; CMOS integrated circuits; CMOS technology; Computer simulation; Corner effects; Corners; Design. Technologies. Operation analysis. Testing; Devices; Doping; Electronics; Exact sciences and technology; FinFETs; Gates (circuits); Integrated circuits; Logic gates; Metals; MOSFETs; Optimization; polysilicon gate; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Transistors; triple-gate (TG) MOSFETs; triple-gate (TG) MOSFETs; Corner effects; polysilicon gate; Performance evaluation; High performance; MOSFET; Potential barrier; Polycrystal; Short channel; n channel; Doping profile; Optimal design; Field effect transistor; Complementary MOS technology; Numerical simulation; Low-power electronics; Comparative study
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2008.927664

Pragmatic design of triple-gate (TG) devices is presented by considering corner effects, short-channel effects, and channel-doping profiles. A novel TG MOSFET structure with a polysilicon gate process is proposed using asymmetrical polysilicon gates. CMOS-compatible 's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed and validated by 3-D numerical simulations. Comparisons of device characteristics with a midgap metal gate are presented.