Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs
Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when str...
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Published in | IEEE electron device letters Vol. 29; no. 3; pp. 262 - 264 |
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Main Authors | , , , |
Format | Journal Article |
Language | English |
Published |
New York, NY
IEEE
01.03.2008
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (V g = V d ), whereby degradation is simultaneously induced by both NBTI and hot carrier injection (HCI) simultaneously ("concurrent HCI-NBTI"), the relative importance of each mechanism depending on the type of device and the bias level. The degradation of I/O pMOSFETs stressed under V g = V d at room temperature shows predominantly NBTI-like behavior at higher stress voltages, whereas it shows concurrent HCI-NBTI behavior at lower stress voltages. By contrast, the degradation of HS pMOSFETs stressed under V g = V d shows concurrent HCI-NBTI behavior over the entire stress bias range. In both cases, FB devices degrade more than GB devices for higher stress voltage values, but the FB effects weaken and the degradations become comparable for lower stress bias. |
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Bibliography: | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
ISSN: | 0741-3106 1558-0563 |
DOI: | 10.1109/LED.2007.915382 |