Dynamic scan: driving down the cost of test

• Published in: Computer (Long Beach, Calif.) Vol. 35; no. 10; pp. 63 - 68
• Main Authors: Samaranayake, S., Sitchinava, N., Kapur, R., Amin, M.B., Williams, T.W.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2002; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Automatic generation control; Automatic test pattern generation; Automatic testing; Benefit cost analysis; Chip formation; Chips; Costs; Design engineering; Design for testability; Driving; Dynamic tests; Dynamics; Fabrication; Flip-flops; Logic testing; Methodology; Product testing; Semiconductor device testing; Semiconductors; Soaring; Test pattern generators
• ISSN: 0018-9162; 1558-0814
• DOI: 10.1109/MC.2002.1039519

Two factors primarily drive the soaring cost of semiconductor test: the number of test patterns applied to each chip and the time it takes to run each pattern. Typical semiconductor testing for each chip involves a set of 1,000 to 5,000 test patterns. These tests are applied through scan chains that operate at about 25 MHz. Depending on the size of the scan chains on the chip, a set of test patterns can take a few seconds to execute per chip. It's easy to see that even a small decrease in either the number of patterns or the time to execute them can quickly add up to big savings across millions of fabricated chips. This potential savings forms the basis for dynamic scan, a new approach to the well-established scan test methodology. The authors initial studies indicate that dynamic scan could easily reduce the time spent applying test patterns by 40 percent. A more theoretical analysis shows a potential savings of as much as 80 percent.