2.7–4.0 GHz PLL with dual-mode auto frequency calibration for navigation system on chip

• Published in: Journal of Central South University Vol. 23; no. 9; pp. 2242 - 2253
• Main Authors: Chen, Zhi-jian, Cai, Min, He, Xiao-yong, Xu, Ken
• Format: Journal Article
• Language: English
• Published: Changsha Central South University 01.09.2016; Springer Nature B.V
• Subjects: Algorithms; Calibration; Capacitor banks; Charge pumps; CMOS; Control Science and Information Engineering; Electric potential; Engineering; Frequency ranges; Locking; Mechanical Engineering; Metallic Materials; Navigation systems; Phase locked loops; Radio frequency; Semiconductors; Switching theory; System on chip; Voltage; Voltage controlled oscillators; lock time; auto frequency calibration; voltage control oscillator; phase lock loop
• ISSN: 2095-2899; 2227-5223
• DOI: 10.1007/s11771-016-3282-y

A 2.7–4.0 GHz dual-mode auto frequency calibration (AFC) fast locking PLL was designed for navigation system on chip (SoC). The SoC was composed of one radio frequency (RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator (VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop (PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor (CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is −90 dBc/Hz@100 kHz frequency offset and −120 dBc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about −142 dBm and −155 dBm, respectively. The area of the proposed PLL is 0.35 mm 2 and the total SoC area is about 9.6 mm 2 .