A VLSI Architecture for the V-BLAST Algorithm in Spatial-Multiplexing MIMO Systems

This paper presents a VLSI architecture for the suboptimal hard-output Vertical-Bell Laboratories Layered Space-Time (V-BLAST) algorithm in the context of Spatial Multiplexing Multiple-Input Multiple-Output (SM-MIMO) systems immersed in Rayleigh fading channels. The design and implementation of its...

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Bibliographic Details
Published inJournal of engineering (Cairo, Egypt) Vol. 2013; no. 2013; pp. 1 - 7
Main Authors Cervantes-Lozano, Pedro, González-Pérez, Luis F., García-García, Andrés D.
Format Journal Article
LanguageEnglish
Published Cairo, Egypt Hindawi Puplishing Corporation 2013
Hindawi Publishing Corporation
Hindawi Limited
Wiley
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Summary:This paper presents a VLSI architecture for the suboptimal hard-output Vertical-Bell Laboratories Layered Space-Time (V-BLAST) algorithm in the context of Spatial Multiplexing Multiple-Input Multiple-Output (SM-MIMO) systems immersed in Rayleigh fading channels. The design and implementation of its corresponding data-path and control-path components over FPGA devices are considered. Results on synthesis, bit error rate performance, and data throughput are reported.
ISSN:2314-4904
2314-4912
2314-4912
DOI:10.1155/2013/534735