Multiple Bus Architectures

By replacing the single shared bus of conventional multiprocessor architectures by a set of buses, the number of processors can be increased to a few hundred. In this article, some of the practicalities of using multiple bus systems instead of single ones are explored. The operation of a hypothetica...

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Bibliographic Details
Published inComputer (Long Beach, Calif.) Vol. 20; no. 6; pp. 42 - 48
Main Authors MUDGE, TREVORN, HAYES, JOHNP, WINSOR, DONALDC
Format Journal Article
LanguageEnglish
Published United States IEEE 01.06.1987
Subjects
990210 - Supercomputers- (1987-1989)
ARRAY PROCESSORS
BAND THEORY
COMPUTER ARCHITECTURE
Computer networks
CONSTRUCTION
Costs
DATA TRANSMISSION
DATA TRANSMISSION SYSTEMS
EQUIPMENT INTERFACES
Fault tolerant systems
GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
Integrated circuit interconnections
MEMORY DEVICES
Multiprocessor interconnection networks
Reliability
SUPERCOMPUTERS
Switches
System buses
System performance
Wiring
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Summary:By replacing the single shared bus of conventional multiprocessor architectures by a set of buses, the number of processors can be increased to a few hundred. In this article, some of the practicalities of using multiple bus systems instead of single ones are explored. The operation of a hypothetical multiple bus system is described, and a simple performance model of such a system is developed. The use of this model and its implications for the design of a multiple bus subsystem are discussed. (C.D.)
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0018-9162
1558-0814
DOI:10.1109/MC.1987.1663590