Optimal Common-Mode Voltage Injection for Phase-Modular Three-Phase PFC Rectifiers Minimizing Energy Buffering Requirement

• Published in: IEEE open journal of power electronics Vol. 4; pp. 1 - 13
• Main Authors: Menzi, David, Marugg, Valentin, Langbauer, Thomas, Kolar, Johann W.
• Format: Journal Article
• Language: English
• Published: IEEE 01.01.2023
• Subjects: Ac-dc converter; Capacitors; CM voltage injection; DC-DC power converters; Harmonic analysis; harmonic injection; modular; PFC rectifier; Rectifiers; three-phase; Voltage; Voltage control; zero sequence
• ISSN: 2644-1314; 2644-1314
• DOI: 10.1109/OJPEL.2023.3308904

Realizing an isolated three-phase Power Factor Correction (PFC) ac-dc converter as a phase-modular system, i.e, by star-connecting three single-phase PFC rectifier front-ends with individual isolated dc-dc converter stages generating a common dc output voltage advantageously facilitates the use of standard single-phase converter modules. Further the low dc-link voltage level of typically <inline-formula><tex-math notation="LaTeX">400 \,\mathrm{V}</tex-math></inline-formula> (for a grid with <inline-formula><tex-math notation="LaTeX">230 \,\mathrm{V}_\mathrm{rms}</tex-math></inline-formula> line-to-neutral voltage) allows to employ high performance <inline-formula><tex-math notation="LaTeX">600 \,\mathrm{V}</tex-math></inline-formula> power semiconductors. The main drawback of this concept, however, is the fact that the time-varying single-phase input power only sums to a constant three-phase output power at the isolated dc output, such that large dc-link capacitor values are required in each module (in the range of several <inline-formula><tex-math notation="LaTeX">100 \,\mathrm{\upmu }\mathrm{F}</tex-math></inline-formula> for a <inline-formula><tex-math notation="LaTeX">6 \,\mathrm{kW}</tex-math></inline-formula> system), thereby limiting the achievable power density. It is known from literature that the dc-link energy buffering requirement <inline-formula><tex-math notation="LaTeX">\mathbf {\Delta \mathit{E}_{\mathrm{dc}}}</tex-math></inline-formula> can be reduced by means of a third-harmonic common-mode (CM) voltage injection modulation and this paper identifies the optimal CM voltage waveform with respect to minimizing <inline-formula><tex-math notation="LaTeX">\mathbf {\Delta \mathit{E}_{\mathrm{dc}}}</tex-math></inline-formula>, i.e., reducing <inline-formula><tex-math notation="LaTeX">\mathbf {\Delta \mathit{E}_{\mathrm{dc}}}</tex-math></inline-formula> to the theoretical minimum by combining a brute-force evaluation of the time-domain CM voltage waveform with phase-symmetry considerations. Additionally, converter operation with minimum dc-link voltage and/or dc-link capacitor values is analyzed and a saturable grid current controller allowing operation of the PFC rectifier front-ends with the optimal CM voltage waveform is investigated. Experimental results with a <inline-formula><tex-math notation="LaTeX">6 \,\mathrm{kW}</tex-math></inline-formula> prototype system yield a reduction in <inline-formula><tex-math notation="LaTeX">\mathbf {\Delta \mathit{E}_{\mathrm{dc}}}</tex-math></inline-formula> by up to <inline-formula><tex-math notation="LaTeX">42 \,\%</tex-math></inline-formula> (compared to conventional sinusoidal modulation), which closely matches the theoretical prediction. Also, PFC rectifier operation with a dc-link voltage level as low as <inline-formula><tex-math notation="LaTeX">285 \,\mathrm{V}</tex-math></inline-formula> (i.e., below the <inline-formula><tex-math notation="LaTeX">325 \,\mathrm{V}_\mathrm{pk}</tex-math></inline-formula> grid line-to-neutral voltage amplitude) and with ultra-low dc-link capacitor values is demonstrated.