Knights Landing: Second-Generation Intel Xeon Phi Product

• Published in: IEEE MICRO Vol. 36; no. 2; pp. 34 - 46
• Main Authors: Sodani, Avinash, Gramunt, Roger, Corbal, Jesus, Ho-Seop Kim, Vinod, Krishna, Chinthamani, Sundaram, Hutsell, Steven, Agarwal, Rajat, Yen-Chen Liu
• Format: Journal Article
• Language: English
• Published: Los Alamitos IEEE 01.03.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Bandwidth allocation; Central Processing Unit; Central processing units; Computer architecture; Computer memory; Energy efficiency; Graphics processing units; high-performance computing; Intel Xeon Phi; Knights Landing; Landing; Mathematical analysis; Memory architecture; Microprocessors; parallel computing; Processors; Program processors; Programming; Resource management; Vectors (mathematics); Workload; Workloads
• ISSN: 0272-1732; 1937-4143
• DOI: 10.1109/MM.2016.25

This article describes the architecture of Knights Landing, the second-generation Intel Xeon Phi product family, which targets high-performance computing and other highly parallel workloads. It provides a significant increase in scalar and vector performance and a big boost in memory bandwidth compared to the prior generation, called Knights Corner. Knights Landing is a self-booting, standard CPU that is completely binary compatible with prior Intel Xeon processors and is capable of running all legacy workloads unmodified. Its innovations include a core optimized for power efficiency, a 512-bit vector instruction set, a memory architecture comprising two types of memory for high bandwidth and large capacity, a high-bandwidth on-die interconnect, and an integrated on-package network fabric. These features enable the Knights Landing processor to provide significant performance improvement for computationally intensive and bandwidth-bound workloads while still providing good performance on unoptimized legacy workloads, without requiring any special way of programming other than the standard CPU programming model.