Timing-Attack-Resistant Acceleration of NTRU Round 3 Encryption on Resource-Constrained Embedded Systems

• Published in: Cryptography Vol. 7; no. 2; p. 29
• Main Authors: Camacho-Ruiz, Eros, Martínez-Rodríguez, Macarena C., Sánchez-Solano, Santiago, Brox, Piedad
• Format: Journal Article
• Language: English
• Published: Basel MDPI AG 01.06.2023
• Subjects: Algorithms; Co-design; Constraints; Cryptography; Cybersecurity; Data encryption; Digital signatures; Efficiency; Embedded systems; Encryption; Field programmable gate arrays; Hardware; hardware security; Intellectual property; IoT; Methods; NTRU; Polynomials; post-quantum cryptography; Quantum computing; Quantum cryptography; resource-constrained devices; Run time (computers); Software; Spain
• ISSN: 2410-387X; 2410-387X
• DOI: 10.3390/cryptography7020029

The advent of quantum computing with high processing capabilities will enable brute force attacks in short periods of time, threatening current secure communication channels. To mitigate this situation, post-quantum cryptography (PQC) algorithms have emerged. Among the algorithms evaluated by NIST in the third round of its PQC contest was the NTRU cryptosystem. The main drawback of this algorithm is the enormous amount of time required for the multiplication of polynomials in both the encryption and decryption processes. Therefore, the strategy of speeding up this algorithm using hardware/software co-design techniques where this operation is executed on specific hardware arises. Using these techniques, this work focuses on the acceleration of polynomial multiplication in the encryption process for resource-constrained devices. For this purpose, several hardware multiplications are analyzed following different strategies, taking into account the fact that there are no possible timing information leaks and that the available resources are optimized as much as possible. The designed multiplier is encapsulated as a fully reusable and parametrizable IP module with standard AXI4-Stream interconnection buses, which makes it easy to integrate into embedded systems implemented on programmable devices from different manufacturers. Depending on the resource constraints imposed, accelerations of up to 30–45 times with respect to the software-level multiplication runtime can be achieved using dedicated hardware, with a device occupancy of around 5%.