FPGA-based active disturbance rejection velocity control for a parallel DC/DC buck converter-DC motor system

• Published in: IET power electronics Vol. 13; no. 2; pp. 356 - 367
• Main Authors: Guerrero, Esteban, Guzmán, Enrique, Linares, Jesús, Martínez, Alberto, Guerrero, Gerardo
• Format: Journal Article
• Language: English
• Published: The Institution of Engineering and Technology 05.02.2020
• Subjects: active disturbance rejection control; angular velocity control; cascading parallel converter; control engineering computing; control system synthesis; DC motor velocity control; DC motors; DC‐DC power convertors; electric machine analysis computing; endogenous disturbances; exogenous disturbances; feedback; field programmable gate arrays; FPGA‐based active disturbance rejection velocity control; generalised proportional–integral‐observers‐based active disturbance rejection controller; linear output feedback controllers; machine control; nonlinear control systems; observers; PI control; Research Article; robust velocity controller; cascading parallel converter; machine control; PI control; active disturbance rejection control; DC motor velocity control; field programmable gate arrays; robust velocity controller; linear output feedback controllers; exogenous disturbances; angular velocity control; endogenous disturbances; DC motors; control system synthesis; DC-DC power convertors; feedback; nonlinear control systems; generalised proportional–integral-observers-based active disturbance rejection controller; FPGA-based active disturbance rejection velocity control; control engineering computing; observers; electric machine analysis computing
• ISSN: 1755-4535; 1755-4543
• DOI: 10.1049/iet-pel.2019.0832

This study deals with the robust velocity controller of a DC motor driven by means of parallel DC/DC buck power converters with equal current distribution, from the perspective of a generalised proportional–integral (GPI)-observers-based active disturbance rejection controller (ADRC). The multivariable system is subject to constant torque load demands and changes in the internal parameters. The linear output feedback controllers actively counteract the exogenous and endogenous disturbances that result from the cascading parallel converter and the DC motor. A rapid prototyping tool is used for synthetising the proposed controller into a field-programmable gate array (FPGA) which is based on Matlab/Simulink and a Xilinx System Generator. The robustness of the proposed ADRC system is analysed. The FPGA-based implementation setup is presented with the purpose of validating the theoretical calculations of the proposed DC motor velocity control.