Low-power FPGA using partially low swing routing architecture

• Published in: Electronics & communications in Japan. Part 3, Fundamental electronic science Vol. 88; no. 11; pp. 11 - 19
• Main Authors: Matsumoto, Yohei, Masaki, Akira
• Format: Journal Article
• Language: English
• Published: Hoboken Wiley Subscription Services, Inc., A Wiley Company 01.11.2005
• Subjects: FPGA; power consumption; routing architecture; voltage swing
• ISSN: 1042-0967; 1520-6440
• DOI: 10.1002/ecjc.20170

Since about 60% of the power consumption in FPGA is in routing, it is most important to reduce the power consumption in routing in order to reduce the overall power consumption in FPGA. In previous research, the reduction of the voltage swing in interconnect routing has been attempted in order to reduce the ED product. In general, low voltage swing of routing degrades the operating speed. Hence, in the present research, a partial reduction of voltage swing in routing is proposed. Also, a routing tool is developed for appropriate routing in the routing architecture with partially reduced voltage swing. Experiments show that the power consumption in routing can be reduced by about 30% without degrading the operating speed if the voltage swing in about 70% of the routing is reduced to half. © 2005 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 88(11): 11–19, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20170