Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

• Published in: Journal of semiconductor technology and science Vol. 14; no. 5; pp. 525 - 536
• Main Authors: An, TaeYoon, Choe, KyeongKeun, Kwon, Kee-Won, Kim, SoYoung
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 01.10.2014
• Subjects: 전기공학; number of gate fingers; parasitic resistance; Cutoff frequency; number of fins; radio frequency (RF); fringe capacitance; fin field-effect transistors (FinFETs)
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/jsts.2014.14.5.525

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (fT). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations. KCI Citation Count: 10