Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation-Part II: CNT Interconnect Optimization

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 30; no. 4; pp. 440 - 448
• Main Authors: Chen, Rongmei, Chen, Lin, Liang, Jie, Cheng, Yuanqing, Elloumi, Souhir, Lee, Jaehyun, Xu, Kangwei, Georgiev, Vihar P., Ni, Kai, Debacker, Peter, Asenov, Asen, Todri-Sanial, Aida
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.04.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Area; Arrays; Carbon; carbon nanotube (CNT) interconnect; carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) array; CNTFETs; Design optimization; Electrodes; energy-delay-product (EDP); Engineering Sciences; Field effect transistors; FinFET SRAM array; FinFETs; Integrated circuit interconnections; Interconnections; Layout; Layouts; Metals; Micro and nanotechnologies; Microelectronics; Multi wall carbon nanotubes; Optimization; Palladium; Performance evaluation; Power consumption; Power efficiency; Power management; Random access memory; read latency; Semiconductor devices; SRAM cells; static noise margin; Static random access memory; write latency; layout; read latency; energy-delay-product (EDP); Area; static noise margin; carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) array; FinFET SRAM array; write latency; carbon nanotube (CNT) interconnect
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2022.3146064

The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a carbon nanotube (CNT) SRAM array composed of the schematically optimized CNFET SRAM and CNT interconnects. We consider the interconnects inside the CNFET SRAM cell composed of metallic single-wall CNT (M-SWCNT) bundles to represent the metal layers 0 and 1 (M0 and M1). We investigate the layout structure of CNFET SRAM cell considering CNFET devices, M-SWCNT interconnects, and metal electrode Palladium with CNT (Pd-CNT) contacts. Two versions of cell layout designs are explored and compared in terms of performance, stability, and power efficiency. Furthermore, we implement a 16 Kbit SRAM array composed of the proposed CNFET SRAM cells, multiwall CNT (MWCNTs) inter-cell interconnects and Pd-CNT contacts. Such an array shows significant advantages, with the read and write overall energy-delay product (EDP), static power consumption, and core area of <inline-formula> <tex-math notation="LaTeX">0.28\times </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">0.52\times </tex-math></inline-formula>, and <inline-formula> <tex-math notation="LaTeX">0.76\times </tex-math></inline-formula> respectively to 7-nm FinFET-SRAM array with copper interconnects, whereas the read and write static noise margins are 6% and 12% respectively larger than the FinFET counterpart.