Influence of solder bump arrangements on molded IC encapsulation

• Published in: Microelectronics and reliability Vol. 54; no. 4; pp. 796 - 807
• Main Authors: Khor, C.Y., Abdullah, M.Z., Lau, Chun-Sean, Leong, W.C., Abdul Aziz, M.S.
• Format: Journal Article
• Language: English
• Published: Kidlington Elsevier Ltd 01.04.2014; Elsevier
• Subjects: Applied sciences; Deformation; Design. Technologies. Operation analysis. Testing; Electronics; Encapsulation; Exact sciences and technology; Integrated circuits; Mathematical models; Packages; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Solders; Stresses; Voids; Encapsulation; Deformation; Pressure distribution; Finite volume method; Numerical method; Microelectronics; Modeling; BGA technology; Finite element method; Integrated circuit bonding; Solder bump; Coding; Electronic packaging; Soldered joint; Integrated circuit; Silicon; Void; Structural analysis
• ISSN: 0026-2714; 1872-941X
• DOI: 10.1016/j.microrel.2013.12.010

[Display omitted] •The scaled-up IC encapsulation was carried out to validate the numerical studies.•A total of five models with solder bump arrangements were studied numerically.•The downward chip deformation resists the EMC flow during the filling process.•Solder bump arrangement crucially influences the deformation and stress of IC chip. This paper presents a fluid–structure interaction (FSI) analysis of ball grid array (BGA) package encapsulation. Real-time and simultaneous FSI analysis is conducted by using finite volume code (FLUENT) and finite element code (ABAQUS), which are coupled with MpCCI. A BGA integrated circuit (IC) package with different solder bump arrangements is considered in this study. In the FSI analysis, effects of solder bump arrangements on pressure distribution, void, deformation, and stress imposed on the IC structures are investigated. The maximum deformation and maximum stress on the silicon chip and solder bumps are evaluated. The findings indicate that the full-array solder bump package encounters lower stress and deformation during encapsulation. The void formation of each solder bump arrangement is examined. Scaled-up encapsulation is performed and the predicted flow front advancements are substantiated by experimental results. Results demonstrate the excellent capability of the proposed modeling tools for predictive trends of IC encapsulation. Thus, better understanding of IC encapsulation is provided to engineers and package designers in the microelectronics industry.