A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures

The authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection str...

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Bibliographic Details
Published inIEEE transactions on parallel and distributed systems Vol. 4; no. 2; pp. 175 - 187
Main Authors Sih, G.C., Lee, E.A.
Format Journal Article
LanguageEnglish
Published IEEE 01.02.1993
Subjects
Computer architecture
Delay
Dynamic scheduling
Hardware
Integrated circuit interconnections
Parallel processing
Partitioning algorithms
Processor scheduling
Scheduling algorithm
Signal processing algorithms
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Summary:The authors present a compile-time scheduling heuristic called dynamic level scheduling, which accounts for interprocessor communication overhead when mapping precedence-constrained, communicating tasks onto heterogeneous processor architectures with limited or possibly irregular interconnection structures. This technique uses dynamically-changing priorities to match tasks with processors at each step, and schedules over both spatial and temporal dimensions to eliminate shared resource contention. This method is fast, flexible, widely targetable, and displays promising performance.< >
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:1045-9219
1558-2183
DOI:10.1109/71.207593