Inventory of silicon signatures induced by CDM event on deep sub-micronic CMOS–BICMOS technologies

The main purpose of this paper is to present typical silicon signatures induced by charged device stress and to discuss the nature of failures. This first inventory is elaborated on advanced CMOS–BICMOS technologies until C32 nm dual oxide. It is well known now, that the CDM stress impacts the whole...

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Published inMicroelectronics and reliability Vol. 50; no. 9; pp. 1388 - 1392
Main Authors Galy, Ph, Dudit, S., Vallet, M., Larre, Ph, Bilinski, M., Petit, E., Beltritti, J., Dray, A., Jimenez, J., Jezequel, F., Chevallier, R., Boutonnat, C., Varo, V.
Format Journal Article Conference Proceeding
LanguageEnglish
Published Kidlington Elsevier Ltd 01.09.2010
Elsevier
Subjects
Applied sciences
Charging
Design. Technologies. Operation analysis. Testing
Devices
Electronics
Exact sciences and technology
Failure
Integrated circuits
Inventories
Oxides
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signatures
Stockpiling
Stresses
BiCMOS technology
Charge carrier trapping
Trench technology
Complementary MOS technology
Electronic packaging
Integrated circuit
Electrostatic discharge
Charged device model
Silicon
Advanced technology
Reliability
Failures
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Summary:The main purpose of this paper is to present typical silicon signatures induced by charged device stress and to discuss the nature of failures. This first inventory is elaborated on advanced CMOS–BICMOS technologies until C32 nm dual oxide. It is well known now, that the CDM stress impacts the whole integrated circuit during the stress and two areas are distinguished: the IO area and the core area. The IO area is the most impacted one due to the collected CDM current which can reach up to one Amps decade of the peak current for a huge package. The core area is impacted by the same stress but not by the same magnitude of this stress. Every chips are stressed by Charged Device Model (CDM) in ESDA standard condition. Some failures can be considered as latent defects for ESD reliability by oxide overstress and/or charge trapping and/or contact impact and/or STI impact as depicted in previous views. At the end, a verification tool is introduced targeting the automatic localization of CDM risks in the design.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0026-2714
1872-941X
DOI:10.1016/j.microrel.2010.07.137