Redundant Local-Loop Insertion for Unidirectional Routing

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 36; no. 7; pp. 1113 - 1125
• Main Authors: Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Cline, Brian, Pan, David Z.
• Format: Journal Article
• Language: English
• Published: IEEE 01.07.2017
• Subjects: Analytical models; Linear programming (LP); Metals; Optimization; redundant local loop (RLL); Routing; Timing; timing analysis; via density; Wires
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2017.2651811

As the semiconductor manufacturing technology continues to scale down to sub-10 nm, unidirectional layout style has become the mainstream for lower metal layers with tight pitches. Conventional redundant via (RV) insertion for yield improvement has become obsolete because unidirectional routing patterns forbid off-track routing, i.e., wire bending, for the metal coverage of RVs. To enhance the yield, redundant local-loop insertion (RLLI) is a new way of inserting RVs due to its compatibility with the unidirectional layout style. This paper proposes the first global optimization engine for RLLI considering advanced manufacturing constraints. Our key contributions include bounded timing impact analysis and evaluation for the local-loop structure, net-based local-loop candidate generation and pruning, an integer linear programming (ILP) formulation and scalable iterative relaxation/linear programming solving (IRLS) with incremental search scheme. Experimental results demonstrate that with bounded timing impact (within 1%), the ILP formulation obtains highest insertion rate while the IRLS with incremental search scheme achieves scalable solutions with competitive solution qualities.