A 1.5-to-3.0GHz Tunable RF Sigma-Delta ADC With a Fixed Set of Coefficients and a Programmable Loop Delay

• Published in: IEEE transactions on circuits and systems. II, Express briefs Vol. 67; no. 9; pp. 1559 - 1563
• Main Authors: Sayed, Alhassan, Badran, Tamer, Louerat, Marie-Minerve, Aboushady, Hassan
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.09.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE); Institute of Electrical and Electronics Engineers
• Subjects: Bandpass; Circuits; Clocks; CMOS; Computer Science; Delay; Delays; Electronics; Engineering Sciences; Figure of merit; Frequency measurement; Frequency modulation; Hardware Architecture; Linearity; loop delay; Oversampling; Resonant frequency; Tunable bandpass sigma-delta; Tuning
• ISSN: 1549-7747; 1558-3791
• DOI: 10.1109/TCSII.2020.3013821

In this brief, we present a tunable bandpass RF Sigma-Delta modulator with a fixed set of feedback DAC coefficients. The sampling frequency, f s , is tuned with the center frequency, f 0 , in order to maintain a fixed normalized center frequency, f 0 /f s . Any variation in the loop delay is compensated to maintain a fixed normalized loop-delay t d /T s . The bandpass Sigma-Delta, reported in this brief, is based on an LC resonator with tunable center frequency from 1.5 to 3.0 GHz and a corresponding sampling frequency from 6.0 to 12.0 GHz. For an oversampling ratio of 64, the ADC achieves the same SNDR of 37 dB and the same Dynamic Range of 45 dB over the complete tuning range. This performance is achieved for a bandwith of 47 MHz at 1.5GHz and a Bandwidth of 93 MHz at 3 GHz. The ADC, fabricated in a 65 nm CMOS process, consumes only 13 mW from a 1.2 V supply. In order to compare this circuit with the state of the art, we use not only the conventional ADC Figure of Merit but we also use a Figure of Merit dedicated to RF circuits. In this case, the measured chip center frequency, noise figure and non-linearity are also taken into account in the comparison.