Impact of virtual substrate quality on performance enhancements in strained Si/SiGe heterojunction n-channel MOSFETs

• Published in: Solid-state electronics Vol. 47; no. 8; pp. 1289 - 1295
• Main Authors: Olsen, S.H., O’Neill, A.G., Norris, D.J., Cullis, A.G., Fobelets, K., Kemhadjian, H.A.
• Format: Journal Article
• Language: English
• Published: Elsevier Ltd 01.08.2003
• Subjects: AFM; Cross-hatching; MOSFETs; Oxide interface roughness; Strained Si/SiGe; TEM; Transconductance; Oxide interface roughness; Cross-hatching; AFM; Strained Si/SiGe; TEM; MOSFETs; Transconductance
• ISSN: 0038-1101; 1879-2405
• DOI: 10.1016/S0038-1101(03)00060-1

The performance of surface channel MOSFET devices is dependent on the Si/SiO 2 interface roughness. This paper examines the performance demonstrated by strained Si/SiGe heterojunction n-channel MOSFET devices (HNMOSFETs) fabricated on ultra-low pressure CVD (ULPCVD) material compared with unstrained Si control devices. The surface channel HNMOSFETs were found to exhibit performance enhancements in terms of transconductance of approximately 135% compared with their Si counterparts. In addition, the electrical characteristics of the HNMOSFETs displayed increased uniformity and improvements in the peak transconductance in excess of 75% compared with equivalent devices fabricated on strained Si/SiGe GS-MBE material. Atomic force microscopy and transmission electron microscopy showed that the favourable characteristics of the ULPCVD strained Si/SiGe devices are due to reduced cross-hatch severity of the ULPCVD material, which is shown to decrease nanoscale roughness at the Si/SiO 2 interface.