Neural Synaptic Weighting With a Pulse-Based Memristor Circuit
A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors...
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Published in | IEEE transactions on circuits and systems. I, Regular papers Vol. 59; no. 1; pp. 148 - 158 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.01.2012
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
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Abstract | A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models. |
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AbstractList | A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law ( v = M ( q ) i ). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear hbox TiO 2 memristor and window-based nonlinear memristor models. A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models. A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law ([Formula Omitted]). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear [Formula Omitted] memristor and window-based nonlinear memristor models. |
Author | Sah, Maheshwar Changju Yang Chua, Leon O. Roska, Tamás Hyongsuk Kim |
Author_xml | – sequence: 1 surname: Hyongsuk Kim fullname: Hyongsuk Kim email: hskim@jbnu.ac.kr organization: Div. of Electron. & Inf. Eng., Chonbuk Nat. Univ., Jeonju, South Korea – sequence: 2 givenname: Maheshwar surname: Sah fullname: Sah, Maheshwar organization: Div. of Electron. & Inf. Eng., Chonbuk Nat. Univ., Jeonju, South Korea – sequence: 3 surname: Changju Yang fullname: Changju Yang organization: Div. of Electron. & Inf. Eng., Chonbuk Nat. Univ., Jeonju, South Korea – sequence: 4 givenname: Tamás surname: Roska fullname: Roska, Tamás email: roska@sztaki.hu organization: Comput. & Autom. Res. Inst., Budapest, Hungary – sequence: 5 givenname: Leon O. surname: Chua fullname: Chua, Leon O. email: chua@eecs.berkeley.edu organization: Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA |
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Snippet | A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit,... |
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SubjectTerms | Adjustability Circuits Computer simulation Integrated circuit modeling Joints Mathematical model memristor Memristors Noise programmable synapse pulse-based processing Resistance Switches Switching Synapses synaptic weight Terminals Titanium dioxide Transistors Weighting |
Title | Neural Synaptic Weighting With a Pulse-Based Memristor Circuit |
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