Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Gain cells have recently been shown to be a viable alternative to static random access memory in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power consumed during periodic refresh operations. Ref...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. II, Express briefs Vol. 61; no. 4; pp. 259 - 263
Main Authors Teman, Adam, Meinerzhagen, Pascal, Giterman, Robert, Fish, Alexander, Burg, Andreas
Format Journal Article
LanguageEnglish
Published New York IEEE 01.04.2014
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Summary:Gain cells have recently been shown to be a viable alternative to static random access memory in low-power applications due to their low leakage currents and high density. The primary component of power consumption in these arrays is the dynamic power consumed during periodic refresh operations. Refresh timing is traditionally set according to a worst-case evaluation of retention time under extreme process variations, and worst-case access statistics, leading to frequent power-hungry refresh cycles. In this brief we present a replica technique for automatically tracking the retention time of a gain-cell-embedded dynamic-random-access-memory macrocell according to process variations and operating statistics, thereby reducing the data retention power of the array. A 2-kb array was designed and fabricated in a mature 0.18-μm CMOS process, appropriate for integration in ultralow power applications, such as biomedical sensors. Measurements show efficient retention time tracking across a range of supply voltages and access statistics, lowering the refresh frequency by more than 5×, as compared with traditional worst-case design.
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ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2014.2305016