Nanometer scale linewidth control during etching of polysilicon gates in high-density plasmas
We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape...
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| Published in | Microelectronic engineering Vol. 69; no. 2; pp. 350 - 357 |
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| Main Authors | , , , , , |
| Format | Journal Article |
| Language | English |
| Published |
Elsevier B.V
01.09.2003
Elsevier |
| Subjects | |
| Online Access | Get full text |
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| Abstract | We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition. |
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| AbstractList | We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition. |
| Author | Pargon, E Detter, X Joubert, O Foucher, J Vallier, L Cunge, G |
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| Cites_doi | 10.1116/1.1367262 10.1116/1.588559 10.1002/sia.740171304 |
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| Copyright | 2003 Distributed under a Creative Commons Attribution 4.0 International License |
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| Keywords | CMOS scaling Gate patterning Critical dimension control Plasma etching |
| Language | English |
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| References | Tanuma, Powell, Penn (BIB7) 1991; 17 Xu, Sun, Chen, Qian, Podlesnik (BIB2) 2001; 19 Bell, Joubert, Vallier (BIB4) 1996; 14 (BIB1) 2001 Vahedi, Cooperberg, Cook, Gottscho (BIB6) 1998 Foucher, Cunge, Vallier, Joubert (BIB3) 2002; 20 Foucher, Cunge, Vallier, Joubert (BIB5) 2001 Foucher (10.1016/S0167-9317(03)00321-6_BIB3) 2002; 20 Tanuma (10.1016/S0167-9317(03)00321-6_BIB7) 1991; 17 Xu (10.1016/S0167-9317(03)00321-6_BIB2) 2001; 19 (10.1016/S0167-9317(03)00321-6_BIB1) 2001 Foucher (10.1016/S0167-9317(03)00321-6_BIB5) 2001 Bell (10.1016/S0167-9317(03)00321-6_BIB4) 1996; 14 Vahedi (10.1016/S0167-9317(03)00321-6_BIB6) 1998 |
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| SubjectTerms | CMOS scaling Critical dimension control Gate patterning Plasma etching |
| Title | Nanometer scale linewidth control during etching of polysilicon gates in high-density plasmas |
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