Nanometer scale linewidth control during etching of polysilicon gates in high-density plasmas

We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape...

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Bibliographic Details
Published inMicroelectronic engineering Vol. 69; no. 2; pp. 350 - 357
Main Authors Joubert, O, Pargon, E, Foucher, J, Detter, X, Cunge, G, Vallier, L
Format Journal Article
LanguageEnglish
Published Elsevier B.V 01.09.2003
Elsevier
Subjects
CMOS scaling
Critical dimension control
Gate patterning
Plasma etching
CMOS scaling
Gate patterning
Critical dimension control
Plasma etching
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Summary:We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition.
Bibliography:SourceType-Scholarly Journals-2
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ObjectType-Conference Paper-1
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ISSN:0167-9317
1873-5568
DOI:10.1016/S0167-9317(03)00321-6