Low power synthesizable register files for processor and IP cores

• Published in: Integration (Amsterdam) Vol. 39; no. 2; pp. 131 - 155
• Main Authors: Müller, M., Simon, S., Gryska, H., Wortmann, A., Buch, S.
• Format: Journal Article
• Language: English
• Published: Elsevier B.V 01.03.2006
• Subjects: Clock gating; Interleaving; IP reuse; Low power design; Register file; Soft macro; Register file; Soft macro; IP reuse; Interleaving; Low power design; Clock gating
• ISSN: 0167-9260; 1872-7522
• DOI: 10.1016/j.vlsi.2004.08.001

In this paper, low power architectures of register files on register-transfer level (RTL) are presented. The proposed architectures are implemented using a standard hardware description language (HDL) and can be synthesized within a commercial semi-custom design flow. The presented register file architectures are ideally suited for synthesizable processor cores or IP blocks. It is shown, that significant power savings of register files can be achieved, if a clock gating scheme for register files different from the one usually applied is used. As an alternative, an architecture with register isolation is presented. The third proposed register file architecture is based on interleaving known from signal processing implementations. Although, interleaving is usually applied to multichannel algorithms, it is shown that this architecture can also be applied to certain single channel cases. Experimental results of all three register file architectures prove that a significant power reduction can be achieved.