A high-resolution multi-phase delay-locked loop with offset locking technique

• Published in: International journal of electronics Vol. 103; no. 10; pp. 1699 - 1712
• Main Authors: Chuang, Chi-Nan, Wu, Chun-Yen, Lin, Tsui-Wei
• Format: Journal Article
• Language: English
• Published: Abingdon Taylor & Francis 02.10.2016; Taylor & Francis LLC
• Subjects: CMOS; Delay; Delay-locked loop; Dynamic link libraries; Electrical engineering; Electronics; high-resolution multi-phase; Integrated circuits; Jitter; Locking; offset locking technique; Offsets; phase-locked loop; Voltage
• ISSN: 0020-7217; 1362-3060
• DOI: 10.1080/00207217.2016.1138524

In this work, we propose a new type of high-resolution delay-locked loop (DLL) which achieves the performance of high-resolution output by offset locking techniques without restrictions of intrinsic delay in the delay cell. Compared to traditional multi-phase clock generator, this architecture has the features of small size, low jitters, low-power consumption and high resolution. This DLL has been fabricated in 0.35 μm complementary metal-oxide-semiconductor (CMOS) process. The measured root-mean-square and peak-to-peak jitters are 2.89 ps and 31.1 ps at 250 MHz, respectively. The power dissipation is 68 mW for a supply voltage of 3.3 V. The maximum resolution of this work is 144 p and the intrinsic delay of 0.35 μm CMOS process is 220 ps. Comparing with intrinsic delay, the improvement of maximum resolution is 34.5%.