High-Efficiency Switched-Capacitor DC-DC Converter with Three Decades of Load Current Range Using Adaptively-Biased PFM

A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efficiency of 80% is implemented in a 0.18 μ m CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed to extend battery runti...

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Bibliographic Details
Published inJournal of low power electronics and applications Vol. 10; no. 1; p. 5
Main Authors Veerabathini, Anurag, Furth, Paul M.
Format Journal Article
LanguageEnglish
Published Basel MDPI AG 01.03.2020
Subjects
adaptive biasing
Bandwidths
Capacitors
CMOS
Design
Efficiency
level shifter
Load
Power management
Pulse frequency modulation
Sensors
switched-capacitor
Topology
Transistors
Voltage controlled oscillators
Voltage converters (DC to DC)
voltage-controlled oscillator (vco)
Wearable computers
Wireless networks
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Summary:A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efficiency of 80% is implemented in a 0.18 μ m CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed to extend battery runtime. An efficiency >70% for load currents in the range of 12 μ A to 17.8 mA is achieved by implementing a novel adaptively-biased pulse frequency modulation (ABPFM) technique in the controller. A symmetric charge-discharge topology with two-phase time interleaving is used as a power stage to reduce the output voltage ripple to <72 mV over the entire load current range.
ISSN:2079-9268
2079-9268
DOI:10.3390/jlpea10010005