A Wide Tuning Range Delay Element for Event-Driven Processing of Low-Frequency Signals in 28-nm FD-SOI CMOS

• Published in: IEEE solid-state circuits letters Vol. 3; pp. 198 - 201
• Main Authors: Gonzalez, Angel, Frappe, Antoine, Larras, Benoit, Kaiser, Andreas, Cathelin, Philippe
• Format: Journal Article
• Language: English
• Published: Piscataway IEEE 01.01.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: CMOS; Continuous-time digital signal processing (CT-DSP); Current measurement; Delays; digital delay; Digital signal processing; Engineering Sciences; Frequency filters; fully depleted silicon-on-insulator (FD-SOI) CMOS; IoT; Leakage; Logic gates; Micro and nanotechnologies; Microelectronics; Power consumption; Power demand; Silicon; SOI (semiconductors); Transistors; Tuning; ultra low-power circuits; Ultra-low-power circuits; FD-SOI CMOS; CT-DSP; Digital delay; IoT
• ISSN: 2573-9603; 2573-9603
• DOI: 10.1109/LSSC.2020.3010877

This letter presents a widely tunable digital delay element suitable for low-power low-frequency continuous-time digital signal processing systems. The design uses features of the 28-nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology to precisely control currents in the pA range and significantly reduce the leakage power. The measured tuning range is significantly larger than prior art covering more than 3 decades from 30 ns to 100 <inline-formula> <tex-math notation="LaTeX">\mu \text{s} </tex-math></inline-formula> making it suitable for CT-DSP low-frequency filters. At 0.7-V supply voltage, the dynamic power consumption is 15 fJ/event with a residual power consumption due to leakage of 14 pW.