Analysis of Analog Capacitor for Mixed Signal Circuits in Merged Dynamic Random Access Memory and Logic Devices

• Published in: Japanese Journal of Applied Physics Vol. 41; no. Part 2, No. 6B; pp. L675 - L677
• Main Authors: Jang, Moon Gyu, Lee, Jung Hwan
• Format: Journal Article
• Language: English
• Published: 15.06.2002
• ISSN: 0021-4922
• DOI: 10.1143/JJAP.41.L675

A poly-insulator-poly (PIP) analog capacitor with a novel structure is fabricated to minimize the number of process steps by adopting an analog device in the merged dynamic random access memory (DRAM) and logic (MDL) process. It has polysilicon as the bottom electrode, which is used as the gate material of the transistor, and W-polycide as the top electrode, which is used as a bit line material in DRAM. The area capacitance without the fringe effect is 0.54 fF/mu m2 and the leakage current is < 1 fA/mu m2. The minimum usable capacitor size without the fringe effect is 27 x 27 mu m2. The voltage coefficients of the 1st and 2nd order are 380 ppm/V and -11 ppm/V2, resp., where those of a conventional analog capacitor manufactured by the standard CMOS process are 300-500 and 10-50 ppm/V2, resp. The matching value is 0.044% in an area of 27 x 27 mu m2, which is an excellent result compared with previous work. 14 refs.