A Precise and Hardware-Efficient Time Synchronization Method for Wearable Wired Networks

• Published in: IEEE sensors journal Vol. 16; no. 5; pp. 1460 - 1470
• Main Authors: Derogarian, Fardin, Canas Ferreira, Joao, Grade Tavares, Vitor M.
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.03.2016; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Access control; Clocks; Delay; hardware implementation; Messages; Networks; Peer-to-peer computing; Protocols; Receivers; Sensors; Synchronism; Synchronization; Time synchronization; Time synchronization protocol; Wearable; wearable wired sensor network; Time synchronization protocol; wearable wired sensor network; hardware implementation
• ISSN: 1530-437X; 1558-1748
• DOI: 10.1109/JSEN.2015.2501645

This paper presents and evaluates a high-precision, one-way, and master-to-slave time synchronization protocol to minimize the clock time skew in low-power wearable sensor networks. The protocol is implemented in the media access control layer, and is based on directly eliminating deterministic delays during transmission from source to destination node, at hardware level. The proposed protocol keeps the one-hop average synchronization error close to the signal propagation delay, and the one-hop peak-to-peak jitter equals to the period of each node's system clock period. Both values grow linearly as the hop count increases. The protocol can achieve synchronization in the range of a few nanoseconds, enough to satisfy the requirements of many applications related to wearable networks, with one-way messages. Both theoretical analysis and experimental results, in wired wearable networks, show that the proposed protocol has a better performance than precision time protocol and a standard timing protocol for both single and multi-hop situations. The proposed approach is simpler, requires no calculations, and exchanges fewer messages. Experimental results obtained with an implementation of the protocol in a 0.35-μm CMOS technology show that this approach keeps the one-hop average clock skew around 4.6 ns and peak-to-peak skew around 50 ns for a system clock frequency of 20 mh.