Performance of thyristor memory device formed by a wet etching process

• Published in: Nanotechnology Vol. 30; no. 3; p. 035205
• Main Authors: Yoo, Jisoo, Oh, Gyujin, Kim, Min-Won, Song, Seung-Hyun, Yoo, Sang-Dong, Shim, Tae-Hun, Kim, Eun Kyu
• Format: Journal Article
• Language: English
• Published: England IOP Publishing 18.01.2019
• Subjects: capacitorless DRAM; TCAD simulation; thyristor memory; wet etching
• ISSN: 0957-4484; 1361-6528
• DOI: 10.1088/1361-6528/aaec5b

Thyristor random access memory without a capacitor has been highlighted for its significant potential to replace current dynamic random access memory. We fabricated a two-terminal (2-T) thyristor by wet chemical etching techniques on n+-p-n-p+ silicon epitaxial layers, which have the proper thicknesses and carrier concentrations, as provided by technology computer-aided design simulation. The etched features such as etch rate, surface roughness, and morphologies, in a potassium hydroxide (KOH) and an isotropic etchant, were compared. The type of silicon etchant strongly affected the etched shapes of the side wall and therefore critically influenced the device performance with varying turn-on voltages. The turn-on voltage of thyristor fabricated with a KOH solution showed a consistent tendency of operation voltage in the range of 2.2-2.5 V regardless of the cell size, while the thyristor formulated with isotropic etchant had an operation voltage which increased from about 2.3-4.4 V as the device dimension decreased from 200 m to 10 m. The optimized 2-T thyristor showed a memory window of about 2 V, a nearly zero-subthreshold swing, and a current on-off ratio of about 104-105.