A 5.3-GB/s embedded SDRAM core with slight-boost scheme

• Published in: IEEE journal of solid-state circuits Vol. 34; no. 5; pp. 661 - 669
• Main Authors: Yamazaki, A., Yamagata, T., Hatakenaka, M., Miyanishi, A., Hayashi, I., Tomishima, S., Mangyo, A., Yukinari, Y., Tatsumi, T., Matsumura, M., Arimoto, K., Yamada, M.
• Format: Journal Article
• Language: English
• Published: IEEE 01.05.1999
• Subjects: Access time; Blocking; Circuit testing; Circuits; CMOS; Frequency; Graphics; Integrated circuits; Large scale integration; Logic circuits; Logic design; MOSFETs; Multimedia; Random access memory; SDRAM; Synchronous; Voltage
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/4.760377

This paper describes a slight-boost scheme to improve a transistor performance in system large-scale integrated circuits, which integrate logic circuits and 1-Tr/1-C DRAMs. In this scheme, an embedded SDRAM core has been developed for graphic and multimedia applications. Its maximum operating frequency is 166 MHz, with a peak data rate of 5.3 GB/s. As well, a fast row-address access time of 22 ns has been achieved. The SDRAM core has been fabricated by means of a 0.3-/spl mu/m quad-polysilicon, triple metal, triple-well CMOS process. This SDRAM core has a block write function, enhanced by a multiselect block write scheme, and a synchronous direct memory-access test circuit has been implemented to reduce the number of test pads.