Exploring the design space of mixed swing quadrail for low-power digital circuits

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 5; no. 4; pp. 388 - 400
• Main Authors: Krishnamurthy, R.K., Carley, L.R.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: Piscataway, NJ IEEE 01.12.1997; Institute of Electrical and Electronics Engineers
• Subjects: Applied sciences; Circuit simulation; Circuit testing; CMOS digital integrated circuits; CMOS process; Delay; Design. Technologies. Operation analysis. Testing; Digital circuits; Electronics; Exact sciences and technology; Fabrication; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Space exploration; Switching circuits; Voltage; Circuit design; Methodology; Integrated circuit; Digital circuit; Power supply; Low power; Optimization
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/92.645065

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2/spl times/ improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 /spl mu/m process are presented to demonstrate up to 2,92/spl times/ energy/operation savings for optimized mixed swing circuits compared to static CMOS.