Implementing Neon: a 256-bit graphics accelerator

High-performance 3D graphics accelerators traditionally require multiple chips on multiple boards. In contrast, Neon-a single chip-performs like a multichip design, accelerating openGL 3D rendering and X11 and windows/NT 2D rendering.

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Bibliographic Details
Published inIEEE MICRO Vol. 19; no. 2; pp. 58 - 69
Main Authors McCormack, J., McNamara, R., Gianos, C., Jouppi, N.P., Dutton, T., Zurawski, J., Seiler, L., Correll, K.
Format Journal Article
LanguageEnglish
Published Los Alamitos IEEE 01.03.1999
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Acceleration
Accelerators
Application specific integrated circuits
Bandwidth
Boards
Chips
Computer graphics
Design
Graphics boards
Logic arrays
Microprocessors
Neon
New technology
Prefetching
Rendering
Rendering (computer graphics)
SDRAM
Software performance
Three dimensional
Two dimensional
Workstations
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Summary:High-performance 3D graphics accelerators traditionally require multiple chips on multiple boards. In contrast, Neon-a single chip-performs like a multichip design, accelerating openGL 3D rendering and X11 and windows/NT 2D rendering.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0272-1732
1937-4143
DOI:10.1109/40.755468