Automating Logic Transformations With Approximate SPFDs

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems Vol. 30; no. 5; pp. 651 - 664
• Main Authors: Yu-Shen Yang, Sinha, Subarna, Veneris, Andreas, Brayton, Robert K
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2011; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Approximation; Computational modeling; Correction; Data structures; debug; Design; Design engineering; Dictionaries; engineering change; Integrated circuit modeling; Logic; logic restructuring; logic rewire; Mathematical model; Mathematical models; Methodology; optimization; Preserves; Sequential circuits; SPFD; Transformations; very large scale integration; Wire
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2011.2110590

During the very large scale integration design process, a synthesized design is often required to be modified in order to accommodate different goals. To preserve the engineering effort already invested, designers seek small logic structural transformations to achieve these logic restructuring goals. This paper proposes a systematic methodology to devise such transformations automatically. It first presents a simulation-based formulation to approximate sets of pairs of functions to be distinguished and avoid the memory/time explosion issue inherent with the original representation. Then, it uses this new data structure to devise the required transformations dynamically without the need of a static dictionary model. The methodology is applied to both combinational and sequential designs with transformations at a single or multiple locations. An extensive suite of experiments documents the benefits of the proposed methodology when compared to existing practices.