A general-purpose processor-per-pixel analog SIMD vision chip

A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a...

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Bibliographic Details
Published inIEEE transactions on circuits and systems. I, Regular papers Vol. 52; no. 1; pp. 13 - 20
Main Authors Dudek, P., Hicks, P.J.
Format Journal Article
LanguageEnglish
Published New York IEEE 01.01.2005
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Analog processor array
Application software
Circuits
CMOS imager
CMOS technology
Image processing
Microprocessors
Pixel
Power dissipation
Silicon
smart sensor
Software prototyping
Very large scale integration
vision chip
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Summary:A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 /spl times/ 21 vision chip is fabricated in a 0.6 /spl mu/m CMOS technology and achieves a cell size of 98.6 /spl mu/m /spl times/ 98.6 /spl mu/m. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2004.840093