A floating-body charge monitoring technique for partially depleted SOI technology

• Published in: International journal of electronics Vol. 91; no. 11; pp. 625 - 637
• Main Authors: Kuang, J. B., Saccamango, M. J., Ratanaphanyarat, S., Chuang, C.-T.
• Format: Journal Article
• Language: English
• Published: London Taylor & Francis Group 01.11.2004; Taylor & Francis
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Integrated circuits; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon on insulator technology; Scalability; Charge carrier; CMOS integrated circuits; CMOS memory circuits; Timing; Monitoring
• ISSN: 0020-7217; 1362-3060
• DOI: 10.1080/00207210412331332961

This paper presents a floating-body charge monitoring technique, which does not require the use of body contacts on the device being monitored. A charge monitor is placed along side with the circuit that is susceptible to the floating-body effects in partially depleted (PD) SOI CMOS circuits. It mimics the circuit topology and operating history of a concerned circuit, specifically the worst-case body voltage of the critical device(s) under consideration. The monitoring is achieved by intentionally triggering a parasitic bipolar current pulse and setting the a state recording latch, which subsequently activates the speed recovering circuitry that compensates the loss of performance at critical circuit nets due to the presence of parasitic bipolar current. Implementation examples are given and described. This technique restores performance and improves timing robustness of the MUX-type and SRAM bit line circuits by minimizing the delay degradation or variation from parasitic bipolar currents.