Prediction of performance and processor requirements in real-time data flow architectures

• Published in: IEEE transactions on parallel and distributed systems Vol. 4; no. 11; pp. 1205 - 1216
• Main Authors: Som, S., Mielke, R.R., Stoughton, J.W.
• Format: Journal Article
• Language: English
• Published: Los Alamitos, CA IEEE 01.11.1993; IEEE Computer Society
• Subjects: Aerospace control; Applied sciences; Computer architecture; Computer science; control theory; systems; Computer systems and distributed systems. User interface; Concurrent computing; Data flow computing; Exact sciences and technology; Flow graphs; Iterative algorithms; Predictive models; Process control; Real time systems; Signal processing algorithms; Software; Processor requirement prediction; Dynamic multiprocessor scheduling; Signal processing; Scheduling; Non preemptive; Periodic; Real time system; Time performance prediction
• ISSN: 1045-9219; 1558-2183
• DOI: 10.1109/71.250100

Presents a new data flow graph model for describing the real-time execution of iterative control and signal processing algorithms on multiprocessor data flow architectures. Identified by the acronym ATAMM, for Algorithm to Architecture Mapping Model, the model is important because it specifies criteria for a multiprocessor operating system to achieve predictable and reliable performance. Algorithm performance is characterized by execution time and iteration period. For a given data flow graph representation, the model facilitates calculation of greatest lower bounds for these performance measures. When sufficient processors are available, the system executes algorithms with minimum execution time and minimum iteration period, and the number of processors required is calculated. When only limited processors are available or when processors fail, performance is made to degrade gracefully and predictably. The user off-line is able to specify tradeoffs between increasing execution time or increasing iteration period. The approach to achieving predictable performance is to control the injection rate of input data and to modify the data flow graph precedence relations so that a processor is always available to execute an enabled graph node. An implementation of the ATAMM model in a four-processor architecture based on Westinghouse's VHSIC 1750A Instruction Set Processor is described.< >