A sliding memory plane array processor

• Published in: IEEE transactions on parallel and distributed systems Vol. 4; no. 6; pp. 601 - 612
• Main Authors: Sunwoo, M.H., Aggarwal, J.K.
• Format: Journal Article
• Language: English
• Published: Los Alamitos, CA IEEE 01.06.1993; IEEE Computer Society
• Subjects: Applied sciences; Communication system control; Computer architecture; Computer science; control theory; systems; Computer systems and distributed systems. User interface; Computer vision; Coprocessors; Exact sciences and technology; Image processing; Pixel; Random access memory; Shape control; Software; Streaming media; Very large scale integration; Computer vision; Parallel algorithm; Array processor; Image processing; Computer architecture; SIMD computer; Parallelism; VLSI architecture; VLSI design; Distributed system; Parallel architecture
• ISSN: 1045-9219
• DOI: 10.1109/71.242162

A mesh-connected single-input multiple-data (SIMD) architecture called a sliding memory plane (SliM) array processor is proposed. Differing from existing mesh-connected SIMD architectures, SliM has several salient features such as a sliding memory plane that provides inter-PE communication during computation. Two I/O planes provide an I/O overlapping capability. Thus, inter-PE communication and I/O overhead can be overlapped with computation. Inter-PE communication time is invisible in most image processing tasks because the computation time is larger than the communication time on SliM. The ability to overlap inter-PE communication with computation, regardless of window size and shape and without using a coprocessor or an on-chip DMA controller is unique to SliM.< >