Experimental Observation and Modeling of the Impact of Traps on Static and Analog/HF Performance of Graphene Transistors
The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristic...
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Published in | IEEE transactions on electron devices Vol. 67; no. 12; pp. 5790 - 5796 |
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Main Authors | , , , , , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.12.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Institute of Electrical and Electronics Engineers |
Subjects | |
Online Access | Get full text |
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Summary: | The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-reduced experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the trap effects on the channel potential within the device. High-frequency (HF) figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and HF applications. |
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ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/TED.2020.3029542 |