Developing a 0.18-micron CMOS process

The authors discuss ways to develop certain modules that are required to generate a new generation of devices and meet targeted goals. They also introduce the integration of low-k material to improve IMD parasitic capacitance.

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Bibliographic Details
Published inIEEE MICRO Vol. 19; no. 5; pp. 16 - 22
Main Authors Haond, M., Basso, M.-T., deCoster, E., Guelen, J., Lair, C.
Format Journal Article
LanguageEnglish
Published Los Alamitos IEEE 01.09.1999
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Capacitance
CMOS
CMOS integrated circuits
CMOS process
CMOS technology
Devices
Electrical engineering
Implants
Manufacturing industries
Manufacturing processes
Modules
MOS devices
Parasitic capacitance
R&D
Research & development
Threshold voltage
Transistors
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Summary:The authors discuss ways to develop certain modules that are required to generate a new generation of devices and meet targeted goals. They also introduce the integration of low-k material to improve IMD parasitic capacitance.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0272-1732
1937-4143
DOI:10.1109/40.798105